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1.2.1 Distortion compensation waveform generating circuit

The deflection distortion compensation waveform for horizontal size system is output from pin

64 of IC601. This waveform is output from 1-bit DAC, with 3.3V pulse waveform with resolu-

tion 25MHz output at pin 64. This pulse waveform is leveled by the low-pass filters R632 and

C622 to obtain the vertical cycle compensation waveform, with the amplitude 1.0 to 1.2Vp-p

and connected to pin5 of IC5J1.

The compensation waveform circuit carries out horizontal size and trapezoid compensation,

side pin compensation, side pin top and bottom compensation, side pin S-shape compensation

and side pin W compensation. (Refer to Compensation Image Diagram in Fig. 22)

The deflection compensation waveform for horizontal phase system is output from pin 57 of

IC601. The pin 57 has 1-bit DAC output and outputs the 3.3V pulse waveform with 25MHz

resolution. This pulse waveform is then leveled by the low-pass filters R619, R614, C604 and

C601 to obtain the vertical cycle waveform, which is then electrically added to the horizontal

system PLL filter (pin 20 of IC601) to carry out the deflection distortion compensation of the

horizontal phase system. It carries out parallelogram distortion compensation and side pin

balance (top and bottom) correction. (Refer to the Compensation Image Diagram in Fig. 22.)

The control of horizontal screen width and the side PCC control are carried out by IC5J1, Q503

and Q504. First, the horizontal width signal and each distortion compensation signal im-

pressed in pin 5 of IC5J1 from pin 64 of IC601 are compared with the AFC pulse signal recti-

fied and fed back to pin 13 of IC5J1. The signals are further compared with the constant-

inclination type saw-tooth wave synchronized with the horizontal cycle created inside IC before

turning into the PWM signal of square wave. This PWM signal output from pin 9 of IC5J1

carries out the above control by driving the Q504 gate. Fig. 8 shows the block diagram of

IC5J1 and Fig. 9 the operation image waveforms.

IC5K1 connected to pin 8 of IC5J1 is a transistor with 2 circuits.

Pins 1 and 3 of IC5K1 are for the base, pin 2 is for GND and pins 4 and 5 are for the collector.

Pin 32 of IC101 connected to pin 3 makes pins 5 and 2 open/short by P-SUS signal.

When P-SUS signal is LOW, pin 8 of IC5J1 is led into GND from pin 5 of IC5K1, and make

SYNC input of IC5J1 LOW. As IC5J1 stops operation without SYNC input, Q504 turns OFF

and horizontal deflecting output stops.

Due to this process, destruction by wrong pulse is prevented when it exceeds in Q502.

The Q503 works as a ripple filter in 215V line and keeps the Q503 emitter voltage constant

even if there is a slight fluctuation in the collector voltage of Q503. The Q503 collector has

215V applied to it, with the emitter output being stable at 203V. This is mainly effective in

dynamic regulation.

The horizontal raster position is adjusted by using Q5A1, Q5A2, VR5A1 and T502. The refer-

ence voltage is obtained from the connecting point of Cs and is then input into pin 2 of T502.

When the emitter voltage in Q5A1 and Q5A2 has the DC level increased by adjusting VR5A1,

the current flows to DY side, causing the raster to move left. Reversely, when the DC level of

the emitter voltage is decreased, the current flows to Q5A2 side, causing the raster to move

right.

The Idy DC level is adjusted by varying the emitter voltage of Q5A1 and Q5A2 at the timing

No. 25 (120kHz/85Hz) using VR5A1, so that the raster position comes at the center of CRT.

The operation image is shown in Fig. 10.

This adjustment, however, is confined to the factory, and is not open to the users.

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